However, employment of the two-phase transfer functions to increase the frame rate by the combination with the complementary internal bus lines explained later. The contact structures between the polysilicon and metal layers are simplified, which makes it easy to employ multi-metal layers to reduce parasitic impedance in transfer of the driving voltages.The wafer with double-epi layers: To form the cross-section structure shown in Figures 2 (b) and (c), a dedicated wafer with n- and p-double epi-layers with gradated concentration profiles is used as the starting material .Three-layer p-well design: An innovative design with three p-well layers is introduced to generate a smoothly changing potential gradient toward the collection gate and to protect the storage CCD channels from migration of generated photoelectrons.
The p-well of each pixel has two holes: a large one at the collection gate is to introduce photoelectrons to the storage CCD channels on the front side; a small one at the drain to collect five percent of the generated photo-electrons to monitor in real time a sudden change in the average brightness, which serves as an index for occurrence of a target event.Curved CCD design: Since the very early development stage of the CCD-ISIS group, a curved design has been introduced to transfer photoelectrons smoothly and swiftly .Microlens array: In design of common imagers, microlens arrays are mainly used to increase the nominal fill factor.
For BSI-ISIS, they contribute to pixel separation for oblique incident light to increase the frame rate.
Wiring layout to minimize RC delay in driving Dacomitinib voltage transfer: Attenuation of driving voltages of the ISIS-V12 is rather high, which limited the maximum frame rate for the full well capacity at 250,000 fps. We developed a simple yet accurate evaluation method to estimate the attenuation of the sensor without time-consuming full-scale circuit simulation .Complementary global bus-lines: An innovative, CCD-specific design is AV-951 introduced to reduce the inductance of the two-phase bus lines. This is required to allow the high frequency current flows needed to drive the ISIS-100M at 100 Mfps.
Among these technologies, the wafer with double-epi layers , the curved CCD design method  and an optimization method of wiring for driving voltage transfer to minimize RC delay  have been explained elsewhere. The present paper only describes the effectiveness of the three-layer p-well design, the microlens array and the CCD-specific complementary bus-line design in increasing the frame rate.4.?Acceleration of Photo-Electrons Transport from the Backside to Collection Gate4.1.